Software engineer transitioning into hardware design and verification. Building a foundation in RTL and UVM — bringing software rigor to silicon.
I'm a Ph.D. student in Computer Science at UT Arlington, pivoting from full-stack software development into RTL design and functional verification. The move is deliberate — hardware is where deep CS fundamentals meet real physical constraints.
My background in systems thinking, test automation, and debugging complex pipelines maps naturally onto verification engineering. I write code that tests code — at the gate level.
Currently building skills in SystemVerilog and UVM methodology while completing my Ph.D. research in intelligent systems. I believe the best verification engineers think like software engineers with hardware intuition.
Designed and simulated a 4-bit arithmetic logic unit in SystemVerilog. Covers ADD, SUB, AND, OR, XOR operations with carry-out and zero flag. Testbench written with directed + randomized stimulus.
Interactive 3D personal portfolio with real-time animations built in Three.js. Custom GLSL shaders and Blender-sculpted assets. Fully front-end rendered for zero-latency performance.
Intraday Tesla stock trend predictor using a hybrid LSTM-XGBoost model. Forecasts close, high, low, MACD, and RSI for daily options signals. Full pipeline: Django + Next.js + automated data feed.
Built and customized AI voice agents at LippyAI for automated business call handling. Integrated hCaptcha for DDoS protection. Managed routing and deployment for production scalability.
Open to hardware internship opportunities · Summer / Fall 2026